Image processing apparatus

ABSTRACT

An image processing apparatus enabling alpha blending or other image processing during bit block transfer (bitblt), wherein the selector  52  selects one of the primitive data S 143,  the image data S 12  and the image data S 147   a  that are used for the host-local transfer, and outputs the data to the alpha blend circuit  53.  According to the control signal S 55,  the alpha blend circuit  53  turns on or turns off alpha blending. The selector  54  selects either the image data S 139  or the image data S 53  and writes the data to the DRAM  147.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to an image processing apparatus,particularly, an imaging processing apparatus characterized byprocessing in data transfer between memories.

[0003] 2. Description of the Related Art

[0004] Computer graphics is frequently utilized in various CAD (ComputerAided Design) systems, amusement equipments, or others. Particularly,along with progress in image processing technology in recent years,systems using three-dimensional computer graphics are rapidly and widelyspread.

[0005] Three-dimensional computer graphics involves frequent access tostorage circuits like DRAM in order to perform real-time processing of alarge amount of image data. For this purpose, rendering circuits andDRAMs are built in a semiconductor chip.

[0006] A rendering circuit, for example, includes an alpha blend circuitin addition to a texture circuit to carry out texture processing. Whenwriting image data to a DRAM, for each pixel data, the alpha blendcircuit mixes the data to be written (source data) and the data readfrom a destination address for writing (destination data), based upon analpha data selected from either the source data or the destination data,and carries out alpha blending to write the mixed data to the aboveaddress.

[0007] Further, a rendering circuit carries out bit block transfer(bitblt) that includes local transfer, namely, data transfer within theDRAM, and host-local transfer, namely data transfer from an externalmemory outside the semiconductor chip to the DRAM.

[0008] In a rendering circuit of the related art, the path for datatransfer in the above bitblt is configured to be independent from thealpha blend circuit.

[0009] Recently, demand for image processing at a higher speedincreases, and it is required to perform alpha blending or other imageprocessing during data transfer in bitblt.

[0010] However, a rendering circuit of the related art cannot meet thisrequirement because in a rendering circuit of the related art, as shownabove, the path for data transfer in bitblt is configured independentlyfrom the alpha blend circuit.

SUMMARY OF THE INVENTION

[0011] An object of the present invention is to provide an imageprocessing apparatus able to perform alpha blending or other imageprocessing in the bit block transfer (bitblt).

[0012] To attain the object, according to a first aspect of the presentinvention, there is provided an image processing apparatus comprising afirst interface for inputting a first image data from a calculationprocessing circuit outside a semiconductor chip, and inputting a secondimage data from an external storage circuit outside the semiconductorchip, a semiconductor storage circuit, a selecting circuit for selectingand outputting one of the first image data, the second image data, and athird image data read from the semiconductor storage circuit, an imageprocessing circuit for selecting and performing either processing theimage data inputted from the selecting circuit to generate and output animage data, or outputting an image data inputted from the selectingcircuit, and a second interface for outputting the image data from theimage processing circuit to the semiconductor storage circuit, whereinthe first interface, the semiconductor storage circuit, the selectingcircuit, the image processing circuit, and the second interface areformed in the same semiconductor chip.

[0013] Function of the first image processing apparatus is as follows.

[0014] First, an explanation will be made of the function whenprocessing the first image data inputted from the calculation processingcircuit and writing the data to the semiconductor storage circuit.

[0015] In this case, the first image data from the calculationprocessing circuit is inputted to the first interface. Then, theselecting circuit selects the first image data and outputs it to theimage processing circuit. After that, the image processing circuitprocesses the first image data and outputs the data to the secondinterface. Then, the second interface outputs the inputted first imagedata to the semiconductor storage circuit.

[0016] Next, function of the first image processing apparatus will bepresented when image data is transferred from the external storagecircuit to the semiconductor storage circuit without image processingbeing performed during data transfer.

[0017] In this case, the first interface inputs the second image datafrom the external storage circuit outside the semiconductor chip formedby the constituent elements of the image processing apparatus. Then, theselecting circuit selects the inputted second image data and outputs itto the image processing circuit. After that, the image processingcircuit outputs the image data inputted from the selecting circuitwithout image processing being performed. Then, the second interfaceoutputs the image data inputted from the image processing circuit to thesemiconductor storage circuit.

[0018] Next, function of the first image processing apparatus will bepresented when image data is transferred from the external storagecircuit to the semiconductor storage circuit while image processing isbeing performed during data transfer.

[0019] In this case, the first interface inputs the second image datafrom the external storage circuit. Then, the selecting circuit selectsthe inputted second image data and outputs it to the image processingcircuit. After that, the image processing circuit processes the secondimage data inputted from the selecting circuit and outputs it. Then, thesecond interface outputs the image data inputted from the imageprocessing circuit to the semiconductor storage circuit.

[0020] Next, function of the first image processing apparatus will bepresented when image data is transferred within the semiconductorstorage circuit without image processing being performed during datatransfer.

[0021] The third image data read from the semiconductor storage circuitis inputted to the selecting circuit. Then, the selecting circuitselects the third image data and outputs it to the image processingcircuit. After that, the image processing circuit outputs the thirdimage data inputted from the selecting circuit without image processingbeing performed. Then, the second interface outputs the image datainputted from the image processing circuit to the semiconductor storagecircuit.

[0022] Next, function of the first image processing apparatus will bepresented when image data is transferred within the semiconductorstorage circuit while image processing is being performed during datatransfer.

[0023] The third image data read from the semiconductor storage circuitis inputted to the selecting circuit. Then, the selecting circuitselects the third image data and outputs it to the image processingcircuit. After that, the image processing circuit outputs the thirdimage data inputted from the selecting circuit while image processing isbeing performed. Then, the second interface outputs the image datainputted from the image processing circuit to the semiconductor storagecircuit.

[0024] Preferably, in the first image processing apparatus, the secondinterface inputs an image data read from a write address of thesemiconductor storage circuit and outputs the same data to the imageprocessing circuit, and the image processing circuit performs imageprocessing using the image data inputted from the second interface andthe image data inputted from the selecting circuit, and generates andoutputs an image data.

[0025] In addition, the first image processing apparatus furthercomprises a texture processing circuit for texture processing of theimage data outputted from the calculation processing circuit, andoutputting the image data as the first image data to the firstinterface.

[0026] Further, in the first image processing apparatus, the imageprocessing circuit performs alpha blending using the image data inputtedfrom the selecting circuit and the image data inputted from the secondinterface.

[0027] To attain the above object, according to a second aspect of thepresent invention, there is provided a second image processing apparatuscomprising an interface for inputting a first image data from acalculation processing circuit outside a semiconductor chip, andinputting a second image data from an external storage circuit outsidethe semiconductor chip, a semiconductor storage circuit, a firstselecting circuit for selecting and outputting either the second imagedata or a third image data read from the semiconductor storage circuit,a second selecting circuit for selecting and outputting either the firstimage data, or the image data selected by the first selecting circuit,an image processing circuit for processing the image data inputted fromthe second selecting circuit and generating an image data, and a thirdselecting circuit for selecting and outputting either the image datagenerated by the image processing circuit, or the image data selectedand outputted by the first selecting circuit, wherein the interface, thesemiconductor storage circuit, the first selecting circuit, the secondselecting circuit, the third selecting circuit, and the image processingcircuit are formed in the same semiconductor chip.

[0028] Function of the second image processing apparatus is as follows.

[0029] First, an explanation will be made of the function whenprocessing the first image data inputted from the calculation processingcircuit and writing the data to the semiconductor storage circuit.

[0030] In this case, the first image data from the calculationprocessing circuit is inputted to the interface. Then, the secondselecting circuit selects the inputted first image data and outputs itto the image processing circuit. After that, the image processingcircuit processes the inputted first image data outputs the data to thethird selecting circuit. Then, the third selecting circuit selects theinputted first image data and outputs it to the semiconductor storagecircuit.

[0031] Next, function of the second image processing apparatus will bepresented when image data is transferred from the external storagecircuit to the semiconductor storage circuit without image processingbeing performed during data transfer.

[0032] The second image data from the external storage circuit isinputted to the first selecting circuit via the interface. Then, thefirst selecting circuit selects the inputted second image data andoutputs it to the third selecting circuit. After that, the thirdselecting circuit outputs the inputted second image data to thesemiconductor storage circuit.

[0033] Next, function of the second image processing apparatus will bepresented when image data is transferred from the external storagecircuit to the semiconductor storage circuit while image processing isbeing performed during data transfer.

[0034] The second image data from the external storage circuit isinputted to the first selecting circuit via the interface. Then, thefirst selecting circuit selects the inputted second image data andoutputs it to the second selecting circuit. Then, the second selectingcircuit selects the inputted second image data and outputs it to theimage processing circuit.

[0035] After that, the image processing circuit processes the inputtedsecond image data and outputs the data to the third selecting circuit.Then the third selecting circuit selects the processed second image dataand outputs it to the semiconductor storage circuit.

[0036] Next, function of the second image processing apparatus will bepresented when image data is transferred within the semiconductorstorage circuit without image processing being performed during datatransfer.

[0037] The image data read from the semiconductor storage circuit isinputted to the first selecting circuit. Then, the first selectingcircuit selects the inputted image data and outputs it to the thirdselecting circuit. After that, the third selecting circuit selects andoutputs the inputted image data to the semiconductor storage circuit.

[0038] Next, function of the second image processing apparatus will bepresented when image data is transferred within the semiconductorstorage circuit while image processing is being performed during datatransfer.

[0039] The third image data read from the semiconductor storage circuitis inputted to the first selecting circuit. Then, the first selectingcircuit selects the inputted third image data and outputs it to thesecond selecting circuit, and then the second selecting circuit selectsthe inputted third image data and outputs it to the image processingcircuit. After that, the image processing circuit outputs the thirdimage data inputted from the third selecting circuit while imageprocessing is being performed. Then, the third selecting circuit selectsthe inputted third image data and outputs to the semiconductor storagecircuit.

[0040] To attain the above object, according to a third aspect of thepresent invention, there is provided a third image processing apparatuscomprising a calculation processing circuit, an external storagecircuit, and a rendering circuit, wherein, the rendering circuitincludes a first interface for inputting a first image data from thecalculation processing circuit, and inputting a second image data fromthe external storage circuit, a semiconductor storage circuit, aselecting circuit for selecting and outputting one of the first imagedata, the second image data, and a third image data read from thesemiconductor storage circuit, an image processing circuit for selectingand performing either processing the image data inputted from theselecting circuit to generate and output an image data, or outputting animage data inputted from the selecting circuit, and a second interfacefor outputting the image data from the image processing circuit to thesemiconductor storage circuit; wherein the first interface, thesemiconductor storage circuit, the selecting circuit, the imageprocessing circuit, and the second interface are formed in the samesemiconductor chip.

[0041] Function of the third image processing apparatus is basically thesame as that of the first image processing apparatus.

[0042] To attain the above object, according to a fourth aspect of thepresent invention, there is provided a fourth image processing apparatuscomprising a calculation processing circuit, an external storagecircuit, and a rendering circuit, wherein, the rendering circuitincludes an interface for inputting a first image data from thecalculation processing circuit, and inputting a second image data fromthe external storage circuit, a semiconductor storage circuit, a firstselecting circuit for selecting and outputting either the second imagedata, or a third image data read from the semiconductor storage circuit,a second selecting circuit for selecting and outputting either the firstimage data, or the image data selected by the first selecting circuit,an image processing circuit for processing the image data inputted fromthe second selecting circuit and generating an image data, and a thirdselecting circuit for selecting and outputting either the image datagenerated by the image processing circuit, or the image data selectedand outputted by the first selecting circuit; wherein the interface, thesemiconductor storage circuit, the first selecting circuit, the secondselecting circuit, the third selecting circuit, and the image processingcircuit are formed in the same semiconductor chip.

[0043] Function of the fourth image processing apparatus is basicallythe same as that of the second image processing apparatus.

BRIEF DESCRIPTION OF THE DRAWINGS

[0044] These and other objects and features of the present inventionwill become clearer from the following description of the preferredembodiments given with reference to the attached drawings, wherein:

[0045]FIG. 1 is a view of a configuration of an image processingapparatus showing the related out the present invention;

[0046]FIG. 2 is a view of an overall configuration of athree-dimensional computer graphics system related to an embodiment ofthe present invention;

[0047]FIG. 3 is a view for explaining a configuration related to alphablending and bit block transfer (bitblt) in the memory I/F circuit shownin FIG. 2;

[0048]FIG. 4 is a view for explaining a configuration related to alphablending and bit block transfer (bitblt) in a memory I/F circuit of athree-dimensional computer graphics system related to a secondembodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0049] Related Art of the Invention

[0050] First, an explanation will be made of an image processingapparatus showing the related out of the invention.

[0051]FIG. 1 is a view of a configuration of an image processingapparatus 301 showing the related out of the present invention.

[0052] As shown in FIG. 1, for example, the image processing apparatus301 comprises a CPU 311, a main memory 312, a video processing unit 339,and a rendering circuit 314.

[0053] The rendering circuit 314 includes a memory I/F circuit 344 and aDRAM 347.

[0054] Note that, there is a not-shown texture processing circuit at thefront stage of the memory I/F circuit 344 and after the CPU 311.

[0055] The rendering circuit 314, for example, includes an I/F 350, anI/F 351, a selector 352, an alpha blend circuit 353, a selector 354 andan I/F 355.

[0056] As shown in FIG. 1, in the image processing apparatus 301, whenperforming alpha blending, the image data outputted from the CPU 311becomes a primitive data S311 after texture processing or so on, and theprimitive data S311 is inputted to the alpha blend circuit 353 throughthe I/F 350.

[0057] Further, a destination data S347 b read out from a write addressof the DRAM 347, and an alpha data are inputted to the alpha blendcircuit 353.

[0058] Then, in the alpha blend circuit 353, the primitive source dataS311, and the destination data S347 b are mixed according to a mixingratio given by the alpha data, and an image data S353 is generated.

[0059] Then, the image data S353 is selected by the selector 354, and iswritten to the write address of the DRAM 347 through the I/F 355.

[0060] Further, in the image processing apparatus 301, when performinglocal transfer (bitblt) in which data is transferred locally within theDRAM 347, the image data read from a source address for transfer isinputted to the selector 352 through the I/F 355, selected by theselector 354, and is outputted to the selector 354. Furthermore, thisimage data is selected by the selector 354, and is written to adestination address for transfer in the DRAM 347 via the I/F 355.

[0061] In addition, in the image processing apparatus 301, whenperforming host-local transfer (bitblt), namely, data is transferredfrom the main memory 312 to the DRAM 347, an image data S312 read fromthe main memory 312 is inputted to the selector 352 through the I/F 350.The image data S312 is selected by the selector 352, and is outputted tothe selector 354. Furthermore, the image data S312 is selected by theselector 354, and is written to the destination address for transfer inthe DRAM 347 via the I/F 355.

[0062] In the image processing apparatus 301 mentioned above, becausethe path for data transfer in bitblt is configured to be independentfrom the alpha blend circuit 353, alpha blending cannot be performedduring data transfer in bitblt.

[0063] First Embodiment

[0064] The present embodiment is related to an embodiment of the firstand third aspects of the invention.

[0065]FIG. 2 is a view of a configuration of a three-dimensionalcomputer graphics system 10 of the present embodiment.

[0066] The three-dimensional computer graphics system 10 describes asolid model by combining triangles (polygons) used as unit figures, anddecides color of each pixel on its screen by drawing the polygons, andperforms rendering for polygons displayed on its display.

[0067] Further, in the three-dimensional computer graphics system 10, inaddition to coordinates (x, y) representing positions in a plane, thecoordinate Z representing depth is also used so as to describethree-dimensional bodies, and one point in the three-dimensional spaceis determined by three coordinates (x, y, z).

[0068] As shown in FIG. 2, in the three-dimensional computer graphicssystem 10, for example, the CPU 11, the main memory 12, the I/Ointerface circuit 13, and the rendering circuit 14 are connected via themain bus 15.

[0069] Further, the three-dimensional computer graphics system 10 has avideo processing unit 139.

[0070] Here, the three-dimensional computer graphics system 10corresponds to the third image processing apparatus of the invention,and the rendering circuit 14 corresponds to the first image processingapparatus of the invention.

[0071] In addition, the CPU 11 corresponds to the calculation processingcircuit, and the main memory 12 to the external storage circuit of thepresent invention.

[0072] Next, function of each constituent element will be explained.

[0073] The CPU 11, for example, reads necessary graphic data from themain memory 12 in accordance with process status of applications, andperforms geometric processing like clipping, lighting, or others for thegraphic data, and generates a polygon rendering data S11 b. The CPU 11outputs the polygon rendering data S11 b to the rendering circuit 14through the main bus 15.

[0074] In addition, the CPU 11 controls image processing in therendering circuit 14.

[0075] Specifically, the CPU 11 generates a control signal S11 a, andoutputs it to the rendering circuit 14, thereby the CPU 11 switches theselection state of a selecting circuit in the memory I/F circuit 144 ofthe rendering circuit 14 as described afterwards to control whetherbitblt or alpha blending will be performed or not.

[0076] The I/O interface circuit 13 inputs polygon rendering data fromthe outside when necessary, and outputs the data to the renderingcircuit 14 through the main bus 15.

[0077] The polygon rendering data includes data (x, y, z, R, G, B,alpha, s, t, q) for each vertex of a polygon.

[0078] Here, (x, y, z) represents the three-dimensional coordinates of avertex of the polygon, and (R, G, B, alpha) represents the red, green,blue luminance at the above coordinates, and their blending values inalpha blending, respectively.

[0079] Regarding data (s, t, q), (s, t) represents homogeneouscoordinates of a corresponding texture, and q represents a homogeneousterm. Further, texture coordinates (u, v) can be obtained by multiplyingthe texture sizes USIZE and VSIZE to “s/q” and “t/q”, respectively. Thetexture data stored in the texture buffer 147 a is accessed using thetexture coordinates (u, v).

[0080] Namely, a polygon rendering data includes physical coordinates,and color and texture data of each vertex of a triangle.

[0081] Next, the rendering circuit 14 will be explained in detail.

[0082] As shown in FIG. 2, the rendering circuit 14 comprises a digitaldifferential analyzer (DDA) setup circuit 141, a triangle DDA circuit142, a texture engine circuit 143, a memory interface (I/F) circuit 144,a CRT control circuit 145, a RAMDAC circuit 146, a DRAM 147, and a SRAM(Static RAM) 148, and these are formed on a single semiconductor chip.Namely, the rendering circuit 14 has a DRAM embedded structure.

[0083] The DRAM 147 corresponds to the semiconductor storage circuit ofthe present invention.

[0084] DRAM 147

[0085] The DRAM 147 functions as a texture buffer 147 a, a displaybuffer 147 b, z buffer 147 c, and a texture color look up table (CLUT)buffer 147 d.

[0086] In DRAM 147, in order to store much data, the indices of indexcolors, and their values in the color look up table are stored in thetexture CLUT buffer 147 d.

[0087] The indices and their values in the color look up table are usedin the texture processing. Specifically, each color of R, G, B of atexture element is usually described by eight bits, thus a textureelement is totally by 24 bits, but this increases the amount of datamuch. For this reason, for example, one color from 256 colors isselected beforehand, and this color data is used in the textureprocessing. Due to this, in case of 256 colors, it can be realized todescribe each texture element by eight bits. Although a table fortransformation from an index to a real color turns necessary, morecompact texture data is still obtainable for a higher and higher textureresolution.

[0088] As a result, compressing the texture data becomes possible andthe internal DRAM can be utilized more efficiently.

[0089] Furthermore, the depth information of an object to be drawn isstored in the DRAM 147 in order to process the hidden surfaces thereofin parallel at the same time with drawing.

[0090] As for methods for storing the display data, the depth data, andthe texture data, the display data is stored sequentially from thebeginning of a memory block, and the depth data is stored next, in theremaining empty region, each type of texture data is stored in asequential address space. Therefore, the texture data can be storedefficiently.

[0091] DDA Setup Circuit 141

[0092] The DDA setup circuit 141 performs setup calculations tocalculate differences along sides of a triangle and in the horizontaldirection for data (z, R, G, B, alpha, s, t, q) represented by thepolygon rendering data S11 b, before the later triangle DDA circuit 142performs linear interpolations using vertex values of a triangle in aphysical coordinate system to find color and depth information of eachpixel inside the triangle.

[0093] In the setup calculation, specifically, the desired variation ofa value in case of unit length movement is calculated by using thevalues of the start point, the end point, and the distance between thesetwo points.

[0094] The DDA setup circuit 141 outputs the calculated variation dataS141 to the triangle DDA circuit 142.

[0095] Triangle DDA Circuit 142

[0096] The triangle DDA circuit 142 calculates the linearly interpolateddata (z, R, G, B, alpha, s, t, q) for each pixel inside the triangle byusing the variation data S141 inputted from the DDA setup circuit 141.

[0097] The triangle DDA circuit 142 outputs data (x, y) and data (z, R,G, B, alpha, s, t, q) at coordinates (x, y) for each pixel to thetexture engine circuit 143 as the DDA data (interpolation data) S142.

[0098] For example, the triangle DDA circuit 142 outputs to the textureengine circuit 143 the DDA data S142 of eight pixels (2×4) located in arectangular and processed in parallel.

[0099] Texture Engine Circuit 143

[0100] The texture engine circuit 143 calculates s/q and t/q, and thetexture coordinates (u, v), and reads the (R, G, B) data from thetexture buffer 147 a by means of pipeline.

[0101] For example, the texture engine circuit 143 processes eightpixels (2×4) located in a rectangular in parallel.

[0102] The texture engine circuit 143 divides the s data by the q data,and the t data by the q data.

[0103] In the texture engine circuit 143, for example, eight not-showndivision circuits are provided, and the division calculations of s/q andt/q for eight pixels are made at the same time.

[0104] Further, the texture engine circuit 143 multiplies the divisionresults s/q and t/q by the texture sizes USIZE and VSIZE, respectively,to generate the texture coordinates (u, v).

[0105] The texture engine circuit 143 outputs a request to the SRAM 148and the DRAM 147 through the memory I/F circuit 144 to read dataincluding the generated texture coordinates (u, v). By reading thetexture data stored in the SRAM 148 or the texture buffer 147 a throughthe memory I/F circuit 144, there is obtained (R, G, B) data S148,namely, the texture data stored at a texture address corresponding todata (s, t).

[0106] Here, as described above, the texture data included in thetexture buffer 147 a is stored in the SRAM 148.

[0107] The texture engine circuit 143 generates new (R, G, B) data bymultiplying one by one the (R, G, B) data in the data S148 with the (R,G, B) data in the DDA data S142 from the preceding triangle DDA circuit142, and generates a pixel data S143 including the generated (R, G, B)data and the (x, y, z, alpha) included in the DDA data S142.

[0108] The texture engine circuit 143 outputs the pixel data S143 to thememory I/F circuit 144.

[0109] Note that texture data associated with a number of reductionrates such as MIPMAP or others are stored in the texture buffer 147 a,and which of these reduction rates will be used is decided by apredetermined algorithm for each triangle.

[0110] In case of the full color mode, the texture engine circuit 143directly uses the (R, G, B) data read from the texture buffer 147 a.

[0111] On the other hand, in case of the index color mode, the textureengine circuit 143 reads out the color look up table (CLUT) preparedbeforehand from the CLUT buffer 147 d, then transfers and stores it tothe built-in SRAM, and obtains the (R, G, B) data corresponding to thecolor index read out from the texture buffer 147 a using this color lookup table.

[0112] Memory I/F Circuit 144 The memory I/F circuit 144 transfers datalocally within the DRAM 147 (local transfer), or transfers data betweenthe main memory 12 and the DRAM 147 (host-local transfer), namely,performs bitblt including the local transfer, the host-local transfer,or others.

[0113] In the present embodiment, when transferring data by the abovebitblt, the memory I/F circuit 144 can perform alpha blending that isdescribed later.

[0114] The memory I/F circuit 144 compares the z data included in theimage data (pixel data) S143 inputted from the texture engine circuit143 with the z data stored in the z buffer 147 c, and makes the judgmentwhether or not the image that is drawn using the inputted image dataS143 is closer to the viewer side than the image written in the displaybuffer 147 b last time. If it is true, the z data stored in the z buffer147 c is updated by the z data corresponding to the image data S143.

[0115] The memory I/F circuit 144 writes the (R, G, B) data stored inthe image data S143 to the display buffer 147 b, after alpha blending isperformed for the (R, G, B) data when necessary. Alpha blending will beexplained in detail later.

[0116] Further, when the memory I/F circuit 144 is requested to readdata including the texture coordinates (u, v) from the texture enginecircuit 143, it reads the (R, G, B) data S148 stored in the DRAM 147 orthe SRAM 148.

[0117] When the memory I/F circuit 144 is requested to read a displaydata from the CRT control circuit 145, it reads out a fixed number ofthe display data from the display buffer 147 b, for example, in unit of8 pixels or 16 pixels.

[0118] Next, a configuration associated with alpha blending and bitbltin the memory I/F circuit 144 will be described specifically.

[0119]FIG. 3 is a view for explaining a configuration associated withalpha blending and bitblt in the memory I/F circuit 144.

[0120] For example, as shown in FIG. 3, the memory I/F circuit 144comprises an I/F (interface) 50, an I/F 51, a selector 52, an alphablend circuit 53, a selector 54, a control circuit 55 and an I/F 56.

[0121] Here, the I/F 50 corresponds to the first interface, the selector52 to the selecting circuit, the alpha blend circuit 53 to the imageprocessing circuit, the I/F 56 to the second interface, the controlcircuit 55 to the control circuit of the present invention,respectively.

[0122] As described above, the polygon rendering data S11 b is generatedin the CPU 11, and the polygon rendering data S11 b is inputted to therendering circuit 14 through the main bus 15. Then, the polygonrendering data S11 b is inputted to the I/F 50 as the primitive dataS143 (that is the first image data of the present invention) after beingprocessed in the DDA setup circuit 141, the triangle DDA circuit 142,and the texture engine circuit 143.

[0123] The I/F 50 outputs the inputted primitive data S143 to theselector 52.

[0124] The image data S12 (that is the second image data of the presentinvention) read out from the main memory 12 and used for the host-localtransfer is inputted to the I/F 50 via the main bus 15.

[0125] The I/F 50 outputs the inputted image data S12 to the selector52.

[0126] According to the control signal (selection signal) from thecontrol circuit 55, the selector 52 selects one of the primitive dataS143, the image data S12, and the image data S147 a (that is the thirdimage data of the present invention) read out from the DRAM 147 and usedfor the local transfer, and outputs the selected image data S52 to thealpha blend circuit 53.

[0127] When the control signal S55 indicates alpha blend ON, the alphablend circuit 53 mixes the image data S52 inputted from the selector 52and the destination data S147 b read out from a write address of theDRAM 147 according to a mixing ratio given by an alpha data included inthe data selected from the image data S52 and the destination data S147b to generate an image data S53, and outputs the data to the selector54.

[0128] When the control signal S55 indicates alpha blend OFF, the alphablend circuit 53 directly outputs the image data S52 inputted from theselector 52 to the selector 54 as the image data S53.

[0129] According to the control signal (selection signal) from thecontrol circuit 55, the selector 54 selects one of the image data S139inputted from the video processing unit 139 via the I/F 51, and theimage data S53 inputted from the alpha blend circuit 53, and writes theselected image data S54 to a write address of the DRAM 147 via the I/F56.

[0130] Note that any other image processing circuits may be used toprocess the image (filtering) instead of the alpha blend circuit 53.

[0131] For example, according to the control signal S11 a from the CPU11, the control circuit 55 controls the alpha blend circuit 53 and theselector 54 to have them perform alpha blending and bitblt using theprimitive data S143.

[0132] In the present embodiment, in bitblt, alpha blending using thetransferred image data is performed according to the controllingoperation of the control circuit 55.

[0133] The operation of the control circuit 55 will be explained indetail in connection with examples of operation of the memory I/Fcircuit 144.

[0134] In the following, operation examples of the memory I/F circuit144 are presented.

FIRST EXAMPLE OF OPERATION

[0135] In this example of operation, alpha blending using the primitivedata S143 will be described.

[0136] In this example, according to the control signal S11 a, thecontrol circuit 55 generates a control signal S55 so that the selector52 selects the primitive data S143, the alpha blend circuit 53 setsalpha blending on, and the selector 54 selects the image data S53.

[0137] Due to this, the primitive data S143 inputted through the I/F 50is selected by the selector 52, and is outputted to the alpha blendcircuit 53 as the image data S52.

[0138] In addition, the destination data S147 b read out from the writeaddress in the DRAM 147, and the alpha data are inputted to the alphablend circuit 53.

[0139] Then, in the alpha blend circuit 53, the image data S52 and thedestination data S147 b are mixed according to a mixing ratio given bythe alpha data, and as a result an image data S56 is generated.

[0140] Then, the image data S53 is selected by the selector 54, and iswritten to the write address of the DRAM 147 through the I/F 56.

SECOND EXAMPLE OF OPERATION

[0141] In this example, an explanation will be made of the case in whichthe host-local transfer from the main memory 12 to the DRAM 147 takesplace without alpha blending being performed during data transfer.

[0142] The image data S12 read out from a source address for transfer inthe main memory 12 is inputted to the selector 52 through the main bus15 and the I/F 50.

[0143] The selector 52 selects the image data S12 and outputs the datato the alpha blend circuit 53 as the image data S52.

[0144] Then, without any image processing, the alpha blend circuit 53outputs the inputted image data S12 (S52) to the selector 54 as theimage data S53.

[0145] The selector 54 selects the image data S53 and writes the data tothe destination address in the DRAM 147 via the I/F 56.

THIRD EXAMPLE OF OPERATION

[0146] In this example, an explanation will be made of the case in whichthe host-local transfer from the main memory 12 to the DRAM 147 takesplace while alpha blending is being performed during data transfer.

[0147] The image data S12 read out from a source address for transfer inthe main memory 12 is inputted to the selector 52 through the main bus15 and the I/F 50.

[0148] Then, the selector 52 selects the image data S12 and outputs thedata to the alpha blend circuit 53 as the image data S52.

[0149] In addition, the destination data S147 b read out from the writeaddress in the DRAM 147, and the alpha data are inputted to the alphablend circuit 53.

[0150] Then, in the alpha blend circuit 53, the image data S52 and thedestination data S147 b are mixed according to a mixing ratio given bythe alpha data, and an image data S56 is generated.

[0151] Then, the image data S53 is selected by the selector 54, and iswritten to the write address of the DRAM 147 through THE I/F 56.

[0152] As a result, when image data is transferred from the main memory12 to the DRAM 147, alpha blending can be performed for both the sourceimage data and the destination data.

FOURTH EXAMPLE OF OPERATION

[0153] In this example, an explanation will be made of the case in whichdata transfer within the DRAM 147 takes place without alpha blendingbeing performed during data transfer.

[0154] Then, the image data S147 a read out from a source address fortransfer in the DRAM 147 is inputted to the selector 52 through the I/F56.

[0155] Then, the selector 52 selects the image data S147 a and outputsthe data to the alpha blend circuit 53 as the image data S52.

[0156] Then, the alpha blend circuit 53 directly outputs the inputtedimage data S52 to the selector 54 as the image data S53.

[0157] Then, the selector 54 selects the image data S53 and writes thedata to the destination address in the DRAM 147 via the I/F 56.

FIFTH EXAMPLE OF OPERATION

[0158] In this example, an explanation will be made of the case in whichdata is transferred within the DRAM 147 while alpha blending is beingperformed.

[0159] The image data S147 a read out from a source address for transferin the DRAM 147 is inputted to the selector 52 through the I/F 56.

[0160] Then, the selector 52 selects the image data S147 a and outputsthe data to the alpha blend circuit 53 as the image data S52.

[0161] Then, the alpha blend circuit 53 directly outputs the inputtedimage data S52 to the selector 54 as the image data S53.

[0162] Then, the selector 54 selects the image data S53 and writes thedata to the destination address in the DRAM 147 via the I/F 56.

[0163] In addition, the destination data S147 b read out from the writeaddress (destination address) in the DRAM 147, and the alpha data areinputted to the alpha blend circuit 53.

[0164] Then, in the alpha blend circuit 53, the image data S52 and thedestination data S147 b are mixed according to a mixing ratio given bythe alpha data, and an image data S56 is generated.

[0165] Then, the image data S53 is selected by the selector 54, and iswritten to the write address of the DRAM 147 through the I/F 56.

[0166] As a result, when image data is transferred within the DRAM 147,alpha blending can be performed for both the source image data and thedestination data.

[0167] CRT Control Circuit 145

[0168] The CRT control circuit 145 generates a display address to bedisplayed on a not-shown CRT in synchronization with given horizontaland vertical synchronization signals, and outputs a request to thememory I/F circuit 144 to read data including the display data from thedisplay buffer 147 b. According to the request, the memory I/F circuit144 reads out a fixed number of the display data from the display buffer147 b. The CRT control circuit 145 has a built-in FIFO (First In FirstOut) circuit for storing the display data read out from the displaybuffer 147 b, and outputs the RGB indices to the RAMDAC circuit 146 atcertain time intervals.

[0169] RAMDAC Circuit 146

[0170] The RAMDAC circuit 146 stores the R, G, B data each correspondingto an index value, and sends digital R, G, B data corresponding to theRGB index values inputted from the CRT controller circuit 145 to anot-shown D/A converter (Digital/Analog Converter) to generate analog R,G, B data. The RAMDAC circuit 146 outputs the generated R, G, B data tothe CRT.

[0171] Next, an example is presented of the overall operation of thethree-dimensional computer graphics system 10 as shown in FIG. 2.

[0172] In the three-dimensional computer graphics system 10, data forgraphic drawing is sent to the rendering circuit 14 through the main bus15 from the main memory 12 in the CPU 11, or from the interface circuit13 accepting graphic indices from the outside.

[0173] Note that, when necessary, coordinate transformation, clipping,lighting, or other geometric processing is performed in the CPU 11 forthe data for graphic drawing.

[0174] The polygon rendering data S11 b is inputted to the DDA setupcircuit 141 of the rendering circuit 14.

[0175] In the DDA setup circuit 141, based upon the polygon renderingdata S11 b, a variation data S141 is generated representing differencesalong sides of a triangle and in the horizontal direction. Specifically,the desired variation of a value in case of unit length movement iscalculated by using the values of the start point, the end point, andthe distance between these two points, and is outputted to the triangleDDA circuit 142 as the variation data S141.

[0176] In the triangle DDA circuit 142, data (z, R, G, B, alpha, s, t,q) linearly interpolated in each pixel inside the triangle is calculatedusing the variation data S141.

[0177] Then, the data (x, y) of each vertex of the triangle, and thecalculated data (z, R, G, B, alpha, s, t, q) are outputted to thetexture engine circuit 143 as the DDA data S142 from the triangle DDAcircuit 142.

[0178] In the texture engine circuit 143, with respect to the data (s,t, q) included in the DDA data S142, the s data is divided by the qdata, and the t data by the q data. Then, the division results s/q andt/q is multiplied by the texture sizes USIZE and VSIZE respectively togenerate the texture coordinates (u, v).

[0179] Next, a request is outputted to the memory I/F circuit 144 toread data including the generated texture coordinates (u, v) from thetexture engine circuit 143, and (R, G, B) data S148 stored in the SRAM148 are read out through the memory I/F circuit 144.

[0180] Next, in the texture engine circuit 143, new (R, G, B) data isgenerated by multiplying one by one the (R, G, B) data in the data S148with the (R, G, B) data in the DDA data S142 from the preceding triangleDDA circuit 142, and a pixel data S143 is generated including thegenerated (R, G, B) data and the (x, y, z, alpha) included in the DDAdata S142.

[0181] The pixel data S143 is sent to the memory I/F circuit 144 fromthe texture engine circuit 143.

[0182] Next, in the memory I/F circuit 144 shown in FIG. 2, according tothe control signal S11 a from the CPU 11, for example, operation asexplained in examples 1 to 5 is carried out, and image data is writtento the DRAM 147.

[0183] Further, when displaying an image on a not-shown CRT, in the CRTcontrol circuit 145, a display address is generated in synchronizationwith given horizontal and vertical synchronization signals, and arequest is outputted to the memory I/F circuit 144 to send the displaydata.

[0184] According to the request, in the memory I/F circuit 144, a fixednumber of the display data is sent to the CRT control circuit 145. Inthe CRT control circuit 145, the display data is stored in a not-shownFIFO (First In First Out) circuit, and the RGB index values are outputto the RAMDAC circuit 146 at certain time intervals.

[0185] As described above, according to the three-dimensional computergraphics system 10, by configuring the memory I/F circuit 144 of therendering circuit 14 as 25 shown in FIG. 3, alpha blending can beperformed in the course of bitblt, and higher speed of image processingis achievable.

[0186] Further, according to the three-dimensional computer graphicssystem 10, by using the memory I/F circuit 144 configured as shown inFIG. 3, an apparatus as compact as the related art is achievable.

[0187] Further, according to the three-dimensional computer graphicssystem 10, by providing a DRAM 147 within the rendering circuit 14, itis possible to have a broader bus width between the memory I/F circuit144 and the DRAM 147, therefore, data transfer at a higher speed betweenthem is achievable.

[0188] Second Embodiment

[0189] The present embodiment is related to an embodiment of the secondand fourth aspects of the invention.

[0190] The three-dimensional computer graphics system of the presentembodiment is basically the same as the three-dimensional computergraphics system 10 of the first embodiment as explained with referenceto FIG. 2, except for the configuration of the memory I/F circuit.

[0191] Next, an explanation is made of the memory I/F circuit of thethree-dimensional computer graphics system of the present embodiment.

[0192]FIG. 4 is a view for explaining a configuration associated withalpha blending and bit block transfer (bitblt) in the memory I/F circuit244 of the present invention.

[0193] For example, as shown in FIG. 4, the memory I/F circuit 244 hasI/Fs (interfaces) 60, 61, 65, selectors 70, 71, 72, an alpha blendcircuit 73, and a control circuit 80.

[0194] Here, the I/F 60 corresponds to the interface, the selector 71 tothe first selecting circuit, the selector 70 to the second selectingcircuit, the selector 72 to the third selecting circuit, the alpha blendcircuit 73 to the image processing circuit of the present invention,respectively.

[0195] In the three-dimensional computer graphics system of the presentembodiment, same as the first embodiment, in the CPU 11, the polygonrendering data S11 b is generated and is inputted to the renderingcircuit 14 via the main bus 15. As shown in FIG. 4, the polygonrendering data S11 b is then inputted to the I/F 60 of the memory I/Fcircuit 244 as the primitive data S143 (the first image data of thepresent invention) after being processed in the DDA setup circuit 141,the triangle DDA circuit 142 and the texture engine circuit 143.

[0196] The I/F 60 outputs the inputted primitive data S143 to theselector 70.

[0197] The image data S12 (that is the second image data of the presentinvention) read out from the main memory 12 and used for the host-localtransfer is inputted to the I/F 60 via the main bus 15.

[0198] The I/F 60 outputs the inputted image data S12 to the selector70.

[0199] According to the control signal S80 (selection signal) from thecontrol circuit 80, the selector 71 selects either the image data S12 orthe image data S147 a read out from the DRAM 147 and used for the localtransfer, and outputs the selected image data S71 to the selector 70 andthe selector 72.

[0200] The selector 70 selects either the primitive data S143, or theimage data S71, and outputs the selected image data S70 to the alphablend circuit 73.

[0201] The alpha blend circuit 73 mixes the image data S70 inputted fromthe selector 70 and the destination data S147 b read out from a writeaddress of the DRAM 147 according to a mixing ratio given by an alphadata included in the data selected from the image data S70 and thedestination data S147 b to generate an image data S73, and outputs thedata to the selector 72.

[0202] According to the control signal S80 (selection signal), theselector 72 selects either the image data S139 inputted from the videoprocessing unit 139 via the I/F 61, or the image data S73 inputted fromthe alpha blend circuit 73, and writes the selected image data S72 to awrite address of the DRAM 147 via the I/F 65.

[0203] Note that any other image processing circuits may be used toprocess the image (filtering) instead of the alpha blend circuit 73.

[0204] For example, according to the control signal S11 a from the CPU11, the control circuit 80 controls the alpha blend circuit 73 and theselectors 70, 71, 72 to have them perform alpha blending and bitbltusing the primitive data S143.

[0205] In the present embodiment, in bitblt, alpha blending using thetransferred image data is performed according to the controllingoperation of the control circuit 80.

[0206] The operation of the control circuit 80 will be explained indetail in connection with examples of operation of the memory I/Fcircuit 244.

[0207] Next, operation examples of the memory I/F circuit 244 arepresented.

FIRST EXAMPLE OF OPERATION

[0208] In this example, alpha blending using the primitive data S143will be described.

[0209] In this example, according to the control signal S11 a, thecontrol circuit 80 generates a control signal S80 so that the selector70 selects the primitive data S143, and the selector 72 selects theimage data S73.

[0210] Due to this, the primitive data S143 inputted through the I/F 60is selected by the selector 70, and is outputted to the alpha blendcircuit 73 as the image data S70.

[0211] In addition, the destination data S147 b read out from the writeaddress in the DRAM 147, and the alpha data are inputted to the alphablend circuit 73.

[0212] Then, in the alpha blend circuit 73, the image data S70 and thedestination data S147 b are mixed according to a mixing ratio given bythe alpha data, and an image data S73 is generated.

[0213] Then, the image data S73 is selected by the selector 54, and iswritten to the write address of the DRAM 147 through the I/F 65.

SECOND EXAMPLE OF OPERATION

[0214] In this example, an explanation will be made of the case in whichthe host-local transfer from the main memory 12 to the DRAM 147 takesplace without alpha blending being performed during data transfer.

[0215] The image data S12 read out from a source address for transfer inthe main memory 12 is inputted to the selector 71 through the main bus15 and the I/F 60.

[0216] The selector 71 selects the image data S12 and outputs the datato the alpha blend circuit 73 as the image data S71.

[0217] The selector 72 selects the image data S71 and writes the data tothe destination address in the DRAM 147 via the I/F 65 as the image dataS72.

THIRD EXAMPLE OF OPERATION

[0218] In this example, an explanation will be made of the case in whichthe host-local transfer from the main memory 12 to the DRAM 147 takesplace while alpha blending is being performed during data transfer.

[0219] The image data S12 read out from a source address for transfer inthe main memory 12 is inputted to the selector 71 through the main bus15 and the I/F 60.

[0220] Then, the selector 71 selects the image data S12 and outputs thedata to the selectors 70 and 72 as the image data S71.

[0221] Then, the selector 70 selects the image data S71 and outputs thedata to the alpha blend circuit 73 as the image data S70.

[0222] In addition, the destination data S147 b read out from the writeaddress in the DRAM 147, and the alpha data are inputted to the alphablend circuit 73.

[0223] Then, in the alpha blend circuit 73, the image data S70 and thedestination data S147 b are mixed according to a mixing ratio given bythe alpha data, and an image data S73 is generated.

[0224] Then, the image data S73 is selected by the selector 72, and iswritten to the write address of the DRAM 147 through the I/F 65.

[0225] As a result, when image data is transferred from the main memory12 to the DRAM 147, alpha blending can be performed for both the sourceimage data and the destination data.

FOURTH EXAMPLE OF OPERATION

[0226] In this example, an explanation will be made of the case in whichdata transfer within the DRAM 147 takes place without alpha blendingbeing performed during data transfer.

[0227] The image data S147 a read out from a source address for transferin the DRAM 147 is inputted to the selector 71 through the I/F 65.

[0228] The selector 71 selects the image data S147 a and outputs thedata to the selectors 70 and 71 as the image data S71.

[0229] Then, the selector 72 selects the image data S71 and writes thedata to the destination address in the DRAM 147 via the I/F 65.

FIFTH EXAMPLE OF OPERATION

[0230] In this example, an explanation will be made of the case in whichdata is transferred within the DRAM 147 while alpha blending is beingperformed.

[0231] The image data S147 a read out from a source address for transferin the DRAM 147 is inputted to the selector 71 through the I/F 65.

[0232] Then, the selector 71 selects the image data S147 a and outputsthe data to the selectors 70 and 72 as the image data S71.

[0233] Then, the selector 70 selects the image data S71 and outputs thedata to the alpha blend circuit 73 as the image data S70.

[0234] In addition, the destination data S147 b read out from the writeaddress (destination address) in the DRAM 147, and the alpha data areinputted to the alpha blend circuit 73.

[0235] Then, in the alpha blend circuit 73, the image data S70 and thedestination data S147 b are mixed according to a mixing ratio given bythe alpha data, and an image data S73 is generated.

[0236] Then, the image data S73 is selected by the selector 72, and iswritten to the write address of the DRAM 147 through the I/F 65.

[0237] As a result, when image data is transferred within the DRAM 147,alpha blending can be performed for both the source image data and thedestination data.

[0238] The overall operation of the three-dimensional computer graphicssystem of the present embodiment is the same as that of thethree-dimensional computer graphics system 10 described in the firstembodiment, except for the memory I/F circuit 244.

[0239] As shown above, according to the three-dimensional computergraphics system of present embodiment, the same effects as that of thefirst embodiment can be obtained.

[0240] Summarizing the effects of the present invention, as shown above,according to the image processing apparatus of the present invention,image processing of the image data being transferred can be performedselectively in the course of bitblt, and higher speed of imageprocessing is achievable.

[0241] While the invention has been described with reference to specificembodiments chosen for purpose of illustration, it should be apparentthat numerous modifications could be made thereto by those skilled inthe art without departing from the basic concept and scope of theinvention.

What is claimed is:
 1. An image processing apparatus comprising a firstinterface for inputting a first image data from a calculation processingcircuit outside a semiconductor chip, and inputting a second image datafrom an external storage circuit outside the semiconductor chip, asemiconductor storage circuit, a selecting circuit for selecting andoutputting one of the first image data, the second image data, and athird image data read from the semiconductor storage circuit, an imageprocessing circuit for selecting and performing either processing theimage data inputted from the selecting circuit to generate and output animage data, or outputting an image data inputted from the selectingcircuit, and a second interface for outputting the image data from theimage processing circuit to the semiconductor storage circuit; whereinthe first interface, the semiconductor storage circuit, the selectingcircuit, the image processing circuit, and the second interface areformed in the same semiconductor chip.
 2. An image processing apparatusas set forth in claim 1, further comprising a controlling circuit forcontrolling the selecting circuit to select the first image data, andthe image processing circuit to process the first image data, when thefirst image data is processed and written to the semiconductor storagecircuit.
 3. An image processing apparatus as set forth in claim 1,further comprising a controlling circuit for controlling the selectingcircuit to select the second image data, and the image processingcircuit to output the second image data inputted from the selectingcircuit, when an image data is transferred from the external storagecircuit to the semiconductor storage circuit without image processingbeing performed during data transfer.
 4. An image processing apparatusas set forth in claim 1, further comprising a controlling circuit forcontrolling the selecting circuit to select the second image data, andthe image processing circuit to process and output the second image datainputted from the selecting circuit, when an image data is transferredfrom the external storage circuit to the semiconductor storage circuitwhile image processing is being performed during data transfer.
 5. Animage processing apparatus as set forth in claim 1, further comprising acontrolling circuit for controlling the selecting circuit to select thethird image data, and the image processing circuit to output the thirdimage data inputted from the selecting circuit, when image data istransferred within the semiconductor storage circuit without imageprocessing being performed during data transfer.
 6. An image processingapparatus as set forth in claim 1, further comprising a controllingcircuit for controlling the selecting circuit to select the second imagedata, and the image processing circuit to process and output the secondimage data inputted from the selecting circuit, when image data istransferred from the external storage circuit to the semiconductorstorage circuit when image processing is being performed during datatransfer.
 7. An image processing apparatus as set forth in claim 1,wherein the second interface inputs an image data read from a writeaddress of the semiconductor storage circuit and outputs the same datato the image processing circuit, the image processing circuit performsimage processing using the image data inputted from the second interfaceand the image data inputted from the selecting circuit, and generatesand outputs an image data.
 8. An image processing apparatus as set forthin claim 1, further comprising a texture processing circuit for textureprocessing of the image data outputted from the calculation processingcircuit, and outputting the image data as the first image data to thefirst interface.
 9. An image processing apparatus as set forth in claim7, wherein the image processing circuit performs alpha blending usingthe image data inputted from the selecting circuit and the image datainputted from the second interface.
 10. An image processing apparatuscomprising an interface for inputting a first image data from acalculation processing circuit outside a semiconductor chip, andinputting a second image data from an external storage circuit outsidethe semiconductor chip, a semiconductor storage circuit, a firstselecting circuit for selecting and outputting either the second imagedata or a third image data read from the semiconductor storage circuit,a second selecting circuit for selecting and outputting either the firstimage data, or the image data selected by the first selecting circuit,an image processing circuit for processing the image data inputted fromthe second selecting circuit and generating an image data, and a thirdselecting circuit for selecting and outputting either the image datagenerated by the image processing circuit, or the image data selectedand outputted by the first selecting circuit; wherein the interface, thesemiconductor storage circuit, the first selecting circuit, the secondselecting circuit, the third selecting circuit, and the image processingcircuit are formed in the same semiconductor chip.
 11. An imageprocessing apparatus as set forth in claim 10, wherein the imageprocessing circuit performs image processing using the image data readfrom a write address of the semiconductor storage circuit and the imagedata inputted from the second interface, and generates and outputs animage data.
 12. An image processing apparatus as set forth in claim 11,wherein the image processing circuit performs alpha blending.
 13. Animage processing apparatus as set forth in claim 10, further comprisinga texture processing circuit for texture processing of the image datagenerated by the calculation processing circuit, and outputting theimage data as the first image data to the interface.
 14. An imageprocessing apparatus comprising a calculation processing circuit, anexternal storage circuit, and a rendering circuit, wherein, therendering circuit comprises a first interface for inputting a firstimage data from the calculation processing circuit, and inputting asecond image data from the external storage circuit, a semiconductorstorage circuit, a selecting circuit for selecting and outputting one ofthe first image data, the second image data, and a third image data readfrom the semiconductor storage circuit, an image processing circuit forselecting and performing either processing the image data inputted fromthe selecting circuit to generate and output an image data, oroutputting an image data inputted from the selecting circuit, and asecond interface for outputting the image data from the image processingcircuit to the semiconductor storage circuit; wherein the firstinterface, the semiconductor storage circuit, the selecting circuit, theimage processing circuit, and the second interface are formed in thesame semiconductor chip.
 15. An image processing apparatus comprising acalculation processing circuit, an external storage circuit, and arendering circuit, wherein, the rendering circuit comprises an interfacefor inputting a first image data from the calculation processingcircuit, and inputting a second image data from the external storagecircuit, a semiconductor storage circuit, a first selecting circuit forselecting and outputting either the second image data, or a third imagedata read from the semiconductor storage circuit, a second selectingcircuit for selecting and outputting either the first image data, or theimage data selected by the first selecting circuit, an image processingcircuit for processing the image data inputted from the second selectingcircuit and generating an image data, and a third selecting circuit forselecting and outputting either the image data generated by the imageprocessing circuit, or the image data selected and outputted by thefirst selecting circuit; wherein the interface, the semiconductorstorage circuit, the first selecting circuit, the second selectingcircuit, the third selecting circuit, and the image processing circuitare formed in the same semiconductor chip.